----------------------------------
-- user code for lcd start
----------------------------------

--	slv_reg0(22)		MSB		lcd_rs signal
--	slv_reg0(23)				lcd_rw signal
--	slv_reg0(24)				lcd data bit 0
--	slv_reg0(25)				lcd data bit 1
--	slv_reg0(26)				lcd data bit 2
--	slv_reg0(27)				lcd data bit 3
--	slv_reg0(28)				lcd data bit 4
--	slv_reg0(29)				lcd data bit 5
--	slv_reg0(30)				lcd data bit 6
--	slv_reg0(31)		LSB		lcd data bit 7
--
--	Please keep in mind that lcd data bit 0 is the MSB of the lcd data bus and it must
--	be connected to the bit 7 of the lcd panel on the board.

	REQUEST_PROC : process( Bus2IP_Clk ) is
	begin
		if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
			if Bus2IP_Reset = '1' then
				Bus2IP_WrCE_delay <= '1';
				Bus2IP_RdCE_delay <= '1';
			else
				Bus2IP_WrCE_delay <= not Bus2IP_WrCE(0);
				Bus2IP_RdCE_delay <= not Bus2IP_RdCE(0);
			end if;
		end if;
	end process REQUEST_PROC;

	Bus2IP_RdReq	<= Bus2IP_RdCE(0) and Bus2IP_RdCE_delay;
	Bus2IP_WrReq	<= Bus2IP_WrCE(0) and Bus2IP_WrCE_delay;

--	The following implements a 6-bit counter that is used during write cycles to the
--	lcd. At the beginning of the write cycle, the counter is loaded with 0x3f and then
--	it is decremented on every rising edge of the clock. A terminal count called
--	ack_count_tc is generated when the count reaches 0x03.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		ack_count <= (others => '0');
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if (Bus2IP_WrReq = '1') then
			ack_count <= (others => '1');
		elsif (Bus2IP_WrCE(0) = '1') then
			ack_count <= ack_count - 1;
		end if;
	end if;
end process;


process (ack_count)
begin
	if (ack_count = "000011") then
		ack_count_tc <= '1';
	else
		ack_count_tc <= '0';
	end if;
end process;

--	The following uses the ack_count_tc signal to generate the OPB acknowledge signal
--	for the write cycle.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		IP2Bus_WrAck_i <= '0';
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		IP2Bus_WrAck_i <= ack_count_tc;
	end if;
end process;

--	The following uses the read request from the OPB to generate the OPB acknowledge
--	signal for the read cycle. The core terminates a read cycle in 2 clocks and returns
--	zeros on the data bus.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		IP2Bus_RdAck_i <= '0';
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if (Bus2IP_RdCE(0) = '1') then
			IP2Bus_RdAck_i <= Bus2IP_RdReq;
		end if;
	end if;
end process;

--	Various lcd interface and ipif user side signals are set in the following section.
--	The MSB of the ack_count counter is used to generate the enable signal (lcd_en) to
--	the lcd panel.

IP2Bus_RdAck 					<= IP2Bus_RdAck_i;
IP2Bus_WrAck 					<= IP2Bus_WrAck_i;
IP2Bus_Error 				<= '0';

lcd_rs					<= slv_reg0(22);
lcd_rw					<= slv_reg0(23);
lcd_data					<= slv_reg0(24 to 31);
lcd_en					<= ack_count(0);

----------------------------------
-- user code for lcd end
----------------------------------