-------------------------------------------------------------------
gen_rst_n_dly : process( MCLK ) 
begin
  if( MCLK'event and MCLK = '1' ) then
    rst_n_dly1 <= rst_n_dly0;
    rst_n_dly0 <= RST_N;
  end if;
end process;

-------------------------------------------------------------------
Fir16b20b_1 : Fir16b20b port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          FSCLK => ALRCLK_latch_l,
          COEFFSEL => COEFFSEL_latch,
          XIN => ldata_sig,
          YOUT => LOUT_sig );

-------------------------------------------------------------------
Fir16b20b_2 : Fir16b20b port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          FSCLK => ALRCLK_latch_r,
          COEFFSEL => COEFFSEL_latch,
          XIN => rdata_sig,
          YOUT => ROUT_sig );

-------------------------------------------------------------------
S_P_1 : S_P port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          SDATA => ADATA_latch,
          LRCLK => ALRCLK_latch_l,
          BCLK => ABCLK_latch,
          LDATA => ldata_sig,
          RDATA => rdata_sig ); 

-------------------------------------------------------------------
P_S_1 : P_S port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          LATCH_L => ALRCLK_latch_l,
          LATCH_R => ALRCLK_latch_r,
          BCLK => ABCLK_latch,
          LDATA => LOUT_sig, 
          RDATA => ROUT_sig, 
          SDATA => DDATA );

-------------------------------------------------------------------
TimingGen_1 : TimingGen port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          ALRCLK => ALRCLK_sig,
          ABCLK => ABCLK_sig,
          AMCLK => AMCLK_sig ); 

-------------------------------------------------------------------
initial_latch_1 : initial_latch port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          ADATA => ADATA,
          ADATAO => ADATA_latch, 
          ABCLK => ABCLK_sig,
          ABCLKO => ABCLK_latch, 
          ALRCLK => ALRCLK_sig,
          ALRCLKO => ALRCLK_latch_l, 
          ALRCLKO2 => ALRCLK_latch_r, 
          COEFFSEL => COEFFSEL,
          COEFFSELO => COEFFSEL_latch); 

-------------------------------------------------------------------
  ALRCLK <= ALRCLK_sig;
  ABCLK <= ABCLK_sig;
  AMCLK <= AMCLK_sig;
  
  DLRCLK <= ALRCLK_sig;
  DBCLK <= ABCLK_sig;
  DMCLK <= AMCLK_sig;
  
          PWDN_N <= '1';
          BYPAS <= '1';
          MODE <= "00";
          FMT <= "00";
          OSR <= '0';
          ML <= '0';
          MC <= '0';
          MD <= '0';