component Fir16b20b
   Port (
          RST_N : In std_logic;
          MCLK : In std_logic;
          FSCLK : In std_logic;
          COEFFSEL : in std_logic;
          XIN : In std_logic_vector(15 downto 0);
          YOUT : Out std_logic_vector(15 downto 0) );
end component;

component S_P
   Port (
          RST_N : In std_logic; 
          MCLK : In std_logic; 
          SDATA : In std_logic;
          LRCLK : In std_logic; 
          BCLK : In std_logic; 
          LDATA : Out std_logic_vector(15 downto 0); 
          RDATA : Out std_logic_vector(15 downto 0) ); 
end component;

component P_S
   Port (
          RST_N : In std_logic; 
          MCLK : In std_logic; 
          LATCH_L : In std_logic; 
          LATCH_R : In std_logic; 
          BCLK : In std_logic;  
          LDATA : In std_logic_vector(15 downto 0); 
          RDATA : In std_logic_vector(15 downto 0); 
          SDATA : Out std_logic );
end component;

component TimingGen
   Port (
          RST_N : In std_logic;
          MCLK : In std_logic;
          ALRCLK : Out std_logic;
          ABCLK : Out std_logic;
          AMCLK : Out std_logic ); 
end component;

component initial_latch
   Port (
          RST_N : In std_logic;
          MCLK : In std_logic;
          ADATA : In std_logic;
          ADATAO : Out std_logic;
          ABCLK : In std_logic;
          ABCLKO : Out std_logic;
          ALRCLK : In std_logic;
          ALRCLKO : Out std_logic;
          ALRCLKO2 : Out std_logic;
          COEFFSEL : In std_logic;
          COEFFSELO : Out std_logic );
end component;

signal ldata_sig : std_logic_vector( 15 downto 0 );
signal rdata_sig : std_logic_vector( 15 downto 0 );
signal LOUT_sig : std_logic_vector(15 downto 0);
signal ROUT_sig : std_logic_vector(15 downto 0);
signal rst_n_dly0 : std_logic;
signal rst_n_dly1 : std_logic;
signal AMCLK_sig : std_logic;
signal ALRCLK_sig : std_logic;
signal ABCLK_sig : std_logic;
signal ADATA_latch : std_logic;
signal ALRCLK_latch_l : std_logic;
signal ALRCLK_latch_r : std_logic;
signal ABCLK_latch : std_logic;
signal COEFFSEL_latch: std_logic;