dummy_low <= '0';
  dummy_high <= '1';
  
-----------------------------------------------
AdrsGen_1 : AdrsGen 
port map (
  CLK => CLK,  
  RST_N => RST_N, 
  FFT_START => FFT_START, 
  FFT_SEL => FFT_SEL_sig, 
  FFT_END => open, 
  PHASE_K       => PHASE_K_sig, 
  PHASE_I       => PHASE_I_sig, 
  FFT_ADDR => FFT_ADDR_sig,
  TRI_ADDR => TRI_ADDR_sig );

-----------------------------------------------
TimingGen_1 : TimingGen 
port map (
  CLK => CLK,  
  RST_N => RST_N, 
  CAP_START => CAP_START, 
  CAP_SEL => CAP_SEL_sig, 
  ALRCLK => ALRCLK_sig,
  ABCLK => ABCLK_sig,
  AMCLK => AMCLK_sig,
  ADDRADC => ADC_ADDR_sig ); 

-------------------------------------------------------------------
S_P_1 : S_P port map (
          RST_N => RST_N,
          MCLK => CLK,
          SDATA => ADATA_latch,
          LRCLK => ALRCLK_latch_l,
          BCLK => ABCLK_latch,
          LDATA => ADC_DATA_sig(15 downto 0), 
          RDATA => open ); 

-------------------------------------------------------------------
initial_latch_1 : initial_latch port map (
          RST_N => RST_N,
          MCLK => CLK,
          ADATA => ADATA,
          ADATAO => ADATA_latch, 
          ABCLK => ABCLK_sig,
          ABCLKO => ABCLK_latch, 
          ALRCLK => ALRCLK_sig,
          ALRCLKO => ALRCLK_latch_l, 
          ALRCLKO2 => ALRCLK_latch_r ); 

-------------------------------------------------------------------
TriRom_1 : TriRom port map (
          CLK => CLK,
          CS_N => dummy_low,
          ADDR => TRI_ADDR_sig,
          DATA => TRI_RD_DATA_sig );

-------------------------------------------------------------------
Ram_0_real : Ram port map (
          CLK => CLK,
          CS_N => CS_0_X_sig,
          WR_N => WR_0_X_sig,
          WRADDR => REAL_WR_ADDR_sig,
          RDADDR => REAL_RD_ADDR_sig,
          WRDATA => REAL_WR_DATA_sig(15 downto 0),
          RDDATA => REAL_RD_DATA_sig(15 downto 0) );

-------------------------------------------------------------------
Ram_0_imag : Ram port map (
          CLK => CLK,
          CS_N => CS_0_X_sig,
          WR_N => WR_0_X_sig,
          WRADDR => IMAG_WR_ADDR_sig,
          RDADDR => IMAG_RD_ADDR_sig,
          WRDATA => IMAG_WR_DATA_sig(15 downto 0),
          RDDATA => IMAG_RD_DATA_sig(15 downto 0) );

-------------------------------------------------------------------
Ram_1_real : Ram port map (
          CLK => CLK,
          CS_N => CS_1_X_sig,
          WR_N => WR_1_X_sig,
          WRADDR => REAL_WR_ADDR_sig,
          RDADDR => REAL_RD_ADDR_sig,
          WRDATA => REAL_WR_DATA_sig(15 downto 0),
          RDDATA => REAL_RD_DATA_sig(15 downto 0) );

-------------------------------------------------------------------
Ram_1_imag : Ram port map (
          CLK => CLK,
          CS_N => CS_1_X_sig,
          WR_N => WR_1_X_sig,
          WRADDR => IMAG_WR_ADDR_sig,
          RDADDR => IMAG_RD_ADDR_sig,
          WRDATA => IMAG_WR_DATA_sig(15 downto 0),
          RDDATA => IMAG_RD_DATA_sig(15 downto 0) );

-------------------------------------------------------------------
RamCtrl_1 : RamCtrl
	port map(
    MCLK         => CLK, 
    RST_X        => RST_N, 
    FFT_ADDR     => FFT_ADDR_sig, 
    CAP_SEL      => CAP_SEL_sig, 
    FFT_SEL      => FFT_SEL_sig, 
    FFT_SEL_EXT      => FFT_SEL_EXT_sig, 
    REAL_RD_ADDR => REAL_RD_ADDR_sig, 
    IMAG_RD_ADDR => IMAG_RD_ADDR_sig, 
    REAL_WR_ADDR => REAL_WR_ADDR_sig, 
    IMAG_WR_ADDR => IMAG_WR_ADDR_sig, 
    PHASE_I => PHASE_I_sig, 
    CS_0_X    => CS_0_X_sig, 
    CS_1_X    => CS_1_X_sig, 
    WR_0_X    => WR_0_X_sig, 
    WR_1_X    => WR_1_X_sig, 
    REAL_RD_DATA => REAL_RD_DATA_sig, 
    IMAG_RD_DATA => IMAG_RD_DATA_sig, 
    REAL_WR_DATA => REAL_WR_DATA_sig, 
    IMAG_WR_DATA => IMAG_WR_DATA_sig, 
    FFT_REAL_RD_DATA => FFT_REAL_RD_DATA_sig, 
    FFT_IMAG_RD_DATA => FFT_IMAG_RD_DATA_sig, 
    FFT_REAL_WR_DATA => FFT_REAL_WR_DATA_sig, 
    FFT_IMAG_WR_DATA => FFT_IMAG_WR_DATA_sig,
    ADC_ADDR => ADC_ADDR_sig, 
    ADC_DATA => ADC_DATA_sig,
    UP_ADDR => UP_ADDR,
    UP_RD_DATA => UP_RD_DATA,
    UP_WR_DATA => UP_WR_DATA,
    UP_OE_N => UP_OE_N,
    UP_WE_N => UP_WE_N,
    UP_IMAG_SEL => UP_IMAG_SEL );

-------------------------------------------------------------------
	butterfly_1 : butterfly
	port map(
    MCLK         => CLK,
    RST_X        => RST_N, 
    PHASE_K       => PHASE_K_sig, 
    TRI_RD_DATA  => TRI_RD_DATA_sig, 
    FFT_REAL_RD_DATA => FFT_REAL_RD_DATA_sig, 
    FFT_IMAG_RD_DATA => FFT_IMAG_RD_DATA_sig, 
    FFT_REAL_WR_DATA => FFT_REAL_WR_DATA_sig, 
    FFT_IMAG_WR_DATA => FFT_IMAG_WR_DATA_sig  
   );

-------------------------------------------------------------------
  ALRCLK <= ALRCLK_sig;
  ABCLK <= ABCLK_sig;
  AMCLK <= AMCLK_sig;

          PWDN_N <= '1';
          BYPAS <= '1';
          MODE <= "00";
          FMT <= "00";
          OSR <= '0';

-------------------------------------------------------------------
gen_UP_ADDR : process( slv_reg0 )
begin 
  for i in 9 downto 0 loop
    UP_ADDR(i) <= slv_reg0(31-i);
  end loop;
end process;
 
    UP_OE_N <= slv_reg0(31-10);
    UP_IMAG_SEL <= slv_reg0(31-11);
    CAP_START <= slv_reg0(31-12);
    FFT_START <= slv_reg0(31-13);
    UP_WE_N <= slv_reg0(31-14);
  
-------------------------------------------------------------------
gen_slv_reg1 : process( UP_RD_DATA )
begin 
  for i in 31 downto 16 loop
    slv_reg1(i) <= UP_RD_DATA(31-i);
  end loop;
  for i in 15 downto 2 loop
    slv_reg1(i) <= '0';
  end loop;
  slv_reg1(1) <= FFT_SEL_EXT_sig;
  slv_reg1(0) <= CAP_SEL_sig;
end process;

-------------------------------------------------------------------
gen_UP_WR_DATA : process( slv_reg2 )
begin 
  for i in 15 downto 0 loop
    UP_WR_DATA(i) <= slv_reg2(31-i);
  end loop;
end process;