-- up_out.vhd
-- by Toshio Iwata
-- This file generates RST signals. 

library ieee;
use ieee.std_logic_1164.all;

entity up_out is
  Port (
       RST : out std_logic);
end up_out;

architecture beh of up_out is

begin

gen_RST : process
begin
   RST <= '1';
   wait for 100 us;
   RST <= '0';
   wait;
end process gen_RST;

end beh;