-- t_fir.vhd
-- by Toshio Iwata May/10/00
-- for FIR Filter
-- Change DIOB to change bit length

entity t_fir is
   generic (
        DIOB : integer := 12 );
end t_fir ;

library ieee ;
  use ieee.std_logic_1164.all ;
  use std.textio.all ;

use work.globals_pkg.all ;

architecture beh of t_fir is

component fir_top
   Port (
          RST : In std_logic;
          FSCLK : In std_logic;
          D_IN : In std_logic_vector(DIOB-1 downto 0);
          MCLK : In std_logic;
          D_OUT : Out std_logic_vector(DIOB-1 downto 0) );
end component;

component clks
   Port (
	  FSCLK : out std_logic;
	  MCLK : out std_logic);
end component;

component datas
   Port (
          D_IN : Out std_logic_vector( DIOB-1 downto 0 ) );
end component;

component up_out
   Port (
	  RST : out std_logic);
end component;

signal d_in_signal : std_logic_vector( DIOB-1 downto 0 );
signal d_in_monitor_signal : std_logic_vector( DIOB-1 downto 0 );
signal d_out_signal : std_logic_vector( DIOB-1 downto 0 );
signal d_out_monitor_signal : std_logic_vector( DIOB-1 downto 0 );
signal rst_signal : std_logic;
signal fsclk_signal : std_logic;
signal mclk_signal : std_logic;

begin

d_in_monitor_signal <= not d_in_signal(DIOB-1) & d_in_signal(DIOB-2 downto 0);
d_out_monitor_signal <= not d_out_signal(DIOB-1) & d_out_signal(DIOB-2 downto 0);

fir_top_1 : fir_top port map (
          RST => rst_signal,
          FSCLK => fsclk_signal,
          D_IN => d_in_signal,
          MCLK => mclk_signal,
          D_OUT => d_out_signal);

clks_1 : clks port map (
     FSCLK => fsclk_signal,
     MCLK => mclk_signal );

datas_1 : datas port map (
     D_IN => d_in_signal );

up_out_1 : up_out port map (
  RST => rst_signal );

MAIN_P: process

begin -- process MAIN_P

wait ;

end process ;  -- MAIN_P
-----------------------------------------------------------------------
end beh ;