-- datas.vhd
-- by Toshio Iwata May/10/00
-- This module asserts data to D_IN
-- Change DIOB to change bit length

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use work.math_pkg.all;
use work.globals_pkg.all;

entity datas is
   generic (
        DIOB : integer := 12 );
   Port (
          D_IN : Out std_logic_vector( DIOB-1 downto 0 ) );
end datas;

architecture beh of datas is

  signal data_tmp : signed( DIOB-1 downto 0 );

begin

gen_D_IN : process
variable first_time : boolean := true;
variable pi : real := 3.14159;
variable t : real := 0.0;
variable rdata : real := 0.0;
variable idata : integer := 0;
begin
  if( first_time ) then
    wait for 10 ns;
    first_time := false;
  end if;
  rdata := sv_amp * (sin( 2.0 * pi * sv_fsig * t ));
  idata := integer(rdata);
  data_tmp <= conv_signed(idata, DIOB);
  for i in DIOB-1 downto 0 loop
    D_IN(i) <= data_tmp(i);
  end loop;
  wait for sv_fsclk_period;
  t := t + sv_fsclk_value;
end process;

end beh;