-- clks.vhd
-- by Toshio Iwata May/10/00
-- This module asserts MCLK and FSCLK

library ieee;
use ieee.std_logic_1164.all;

use work.math_pkg.all;
use work.globals_pkg.all;

entity clks is
   Port (
          FSCLK : out std_logic;
          MCLK : out std_logic);
end clks;

architecture beh of clks is

begin

gen_MCLK : process
begin
  MCLK <= '0';
  wait for sv_mclk_period / 2.0;
  MCLK <= '1';
  wait for sv_mclk_period / 2.0;
end process;

gen_FSCLK : process
variable first_time : boolean := true;
begin
  if( first_time ) then 
    wait for 7 ns;
    first_time := false;
  end if; 
  FSCLK <= '1';
  wait for sv_fsclk_period / 2.0;
  FSCLK <= '0';
  wait for sv_fsclk_period / 2.0;
end process;

end beh;