component nios2e is
        port (
            clk_clk                          : in  std_logic                    := 'X';             -- clk
            reset_reset_n                    : in  std_logic                    := 'X';             -- reset_n
            pio_1_external_connection_export : in  std_logic_vector(1 downto 0) := (others => 'X'); -- export
            pio_0_external_connection_export : out std_logic_vector(1 downto 0)                     -- export
        );
    end component nios2e;