--------------------------------------------------
-- RomW8.vhd
-- Synchronous ROM
-- by Toshio Iwata at digitalfilter.com 2019/02/13

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;

entity RomW8 is
   generic (
        DIOB : integer := 9;
        ADDB : integer := 6 );
   Port (
          CLK : In std_logic;
          CS_N : In std_logic;
          ADDR : In std_logic_vector(ADDB-1 downto 0);
          DATA : Out std_logic_vector(DIOB-1 downto 0) );
end RomW8;

architecture RTL of RomW8 is

  subtype ROMWORD is std_logic_vector(DIOB-1 downto 0);
  type ROMARRAY is array (0 to 2**ADDB - 1) of ROMWORD;
  signal ROMDATA : ROMARRAY;
  signal addr_int : integer range 0 to 2**ADDB - 1;
  signal addr_sig : unsigned(ADDB-1 downto 0);

begin

-------------------------------------------------------------------
gen_addr_sig : process( ADDR )
begin 
  for i in ADDB-1 downto 0 loop
    addr_sig(i) <= ADDR(i);
  end loop;
end process gen_addr_sig;

--------------------------------------------------------------
  addr_int <= conv_integer(addr_sig);

--------------------------------------------------------------
rd_data : process(CLK) 
begin 
  if(CLK'event and CLK = '1') then
    if(CS_N = '0') then
      DATA <= ROMDATA(addr_int);
    end if;
  end if;
end process rd_data;

